Antikode RV-32IM Core v1.2 — silicon-proven on TSMC 22ULL assaa
Our flagship 32-bit RISC-V core hits 480 MHz worst-case at 0.72 V on TSMC 22ULL with a 2.1 CoreMark/MHz score. v1.2 ships with hardened debug, JTAG-PMP, and an updated UVM testbench.
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Two years after the first RV-32IM tape-out, we are releasing version 1.2 of the Antikode RV-32IM core — our embedded 32-bit RISC-V implementation targeting low-power MCU and edge-control applications. v1.2 is silicon-proven on TSMC 22ULL with two production tape-outs at customer foundry slots in Q1 2026.
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Headline numbers: 480 MHz worst-case at 0.72 V (SS, 125 °C), 1.05 GHz typical at 0.9 V, 2.1 CoreMark/MHz, and a fully synthesisable footprint of 38 kGE without the optional MAC unit. Dynamic power on the Dhrystone loop measures 6.4 µW/MHz on TSMC 22ULL — a 14% improvement over v1.1 at the same PVT corner.
The micro-architecture is a 5-stage in-order pipeline with single-cycle multiply, an iterative divider, and a configurable instruction prefetch buffer (1, 2, or 4 entries). The optional B extension (Zba/Zbb/Zbs) is now first-class instead of a contributed patch. Interrupt latency is deterministic at 11 cycles for the fast-IRQ path.
What is new in v1.2
JTAG-PMP integration so the debugger respects physical memory protection regions — useful for shipping cores into automotive Tier-2 builds where the debug surface is part of the security model. A reworked UVM testbench with 96.4% functional coverage and a regression suite that runs the full RISC-V Architecture Test Suite plus 240 internally-developed corner cases. Improved power-gating support for sub-domain shutdown during sleep, with retention flops on the architectural register file.
Existing licensees on v1.1 can upgrade with no RTL-level breaking changes; the bus signals, debug interface, and trace ports are pin-compatible. New evaluation requests are open for design-ins targeting Q3 2026 tape-outs onward — request a datasheet and evaluation NDA via the contact form.
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